Hardware Interrupts

  • Interrupts the flow of execution
  • Hardware devices signal via interrupt request (IRQ) when they need attention
  • Sending
    1. Device raises line to interrupt controller
    2. Controller sends interrupt to CPU
    3. CPU acks interrupt (via a signal back to the controller)
      • Checks for interrupt before each instruction fetch and then acks when it is able to handle it
    4. Controller sends IRQ number
  • Processing
    1. Current instruction of process gets interrupted,
      • Switch to kernel mode
    2. Interrupt Dispatcher (IRQ vector table)
    3. Interrupt Handler (Kernel code)
    4. Return control to user mode
  • On multicore systems, the interrupt controller can be programmed to send different interrupts to different processor cores
  • Interrupts are a type of asynchronous trap
  • Almost all peripherals used to require separate interrupts (which led to a maximum amount working at once) but now USB has moved some stuff to software which has made handling many things at once easier

Interrupting an Interrupt

  • Interrupt mask
    • Part of the interrupt controller architecture
    • It is a binary value (mask) stored on a register
    • For each device connected to the interrupt controller, has a hierarchy of other interrupts that are able to interrupt the interrupts
    • Ignored interrupts typically just stay raised
    • Previous interrupts must be restored when the interrupt is complete
      • Remember the old mask values and restore them
      • Most architectures have a dedicated register for this

Precise vs Imprecise Interrupts

  • Precise
    • PC is saved in a known state
    • All instructions preceding interrupt were fully executed
    • No instructions after the PC have been executed
    • Execution state of PC instruction is known
  • Imprecise
    • If instructions are left incomplete/partially executed
    • Caused by Pipelining
    • Makes the hardware much more complicated to interrupt, but is much faster
  • Modern processors have precise interrupts because they wait for the pipeline to empty before running the interrupt
    • Imprecise is only used if it is required for it to be extremely fast