Hardware devices signal via interrupt request (IRQ) when they need attention
Sending
Device raises line to interrupt controller
Controller sends interrupt to CPU
CPU acks interrupt (via a signal back to the controller)
Checks for interrupt before each instruction fetch and then acks when it is able to handle it
Controller sends IRQ number
Processing
Current instruction of process gets interrupted,
Switch to kernel mode
Interrupt Dispatcher (IRQ vector table)
Interrupt Handler (Kernel code)
Return control to user mode
On multicore systems, the interrupt controller can be programmed to send different interrupts to different processor cores
Interrupts are a type of asynchronous trap
Almost all peripherals used to require separate interrupts (which led to a maximum amount working at once) but now USB has moved some stuff to software which has made handling many things at once easier
Interrupting an Interrupt
Interrupt mask
Part of the interrupt controller architecture
It is a binary value (mask) stored on a register
For each device connected to the interrupt controller, has a hierarchy of other interrupts that are able to interrupt the interrupts
Ignored interrupts typically just stay raised
Previous interrupts must be restored when the interrupt is complete
Remember the old mask values and restore them
Most architectures have a dedicated register for this
Precise vs Imprecise Interrupts
Precise
PC is saved in a known state
All instructions preceding interrupt were fully executed
No instructions after the PC have been executed
Execution state of PC instruction is known
Imprecise
If instructions are left incomplete/partially executed