Clocks

• A free-running signal with a fixed cycle time
• Decides when an element in Sequential Logic that contains state should be updated
• Needed because transistors are special capacitors, so it takes time for them to charge and discharge

Using in VHDL

• Clock can be any signal
• Detecting rising edge
  • if(rising_edge(clock)) then
  • if(clock = '1' and clock'event) then

Clock Dividers

• Makes the frequency of a clock slower
• Counts the number of rising edges before switching

$$\frac{\frac{\text{base clock freq}}{2}}{\text{target clock freq}}$$

Relationship to State Elements

• Clock cycle must be long enough that all signals in the Combinational Logic block stabilize
• Inputs are and outputs to combinational logic blocks are state elements
  • when those state elements are read is determined by the clock

Clocking Methodology

• Approach used to determine when the data is valid and stable relative to the clock
• We use Edge Triggered Clocking
  • All state changes occur on a clock edge
  • The simplest to understand
• Read happen on rise, write on fall
  • Prevents race conditions of them happening at the same time