XMEGA

We have an ATxmega128A1U

Nonvolatile program and dat memories
- 128Kb of in-system self-programmable flash
- 8Kb boot section
- 2Kb EEPROM
- 8Kb internal SRAM
External bus interface for up to 16Mbyte SRAM
External bus interface for up to 128Mbit SDRAM

Registers

32 general purpose registers
Last 6 point to data memory
- The X, Y, and Z registers can form 16-bit address pointers for addressing of the Data Memory
- The Z-register can also be used as an address pointer to read/write to the Flash Program Memory, Fuses, Signature Rows, and Lock Bits
RAMP: Extended Indirect Registers
- In order to access program memory or data memory above 64HB the address pointer must be larger than 16 bits
- This is done by concatenating one register to one of the X-, Y-, or Z- registers
  - This register (RAMPX, RAMPY, or RAMPZ) holds the MSB in a 24-bit address or address pointer (224 = 16M, 216 = 64k)
Flags
- SREG: Status register
  - Contains information about the result of the result of the most recently executed arithmetic or logic instruction
  - Updated after all ALU operations
  - The Status Register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt (unlike many other uP’s)
  - The Status Register is accessible in the I/O Memory space
- C: Carry flag
- Z: Zero flag
- N: Negative flag
- V: Two’s complement overflow indicator
- S: N XOR V (for signed tests)
- H: Half carry flag
- T: Transfer bit used by BLD and BST instructions
- I: Global Interrupt Enable/Disable Flag

Four-channel DMA controller
Eight channel event system
Eight 16-bit timer/counters
- Four timer/counters with 4 output compare or input capture channels
- Four timer/counters with 2 output compare or input capture channels
Eight USARTs with IrDA support for one USART
Four two-wire interfaces with dual address match (I2C and SMBus compatible)
Four serial peripheral interfaces (SPIs), i.e., synchronous serial
Two sixteen channel, 12-bit, 2msps ADCs (msps = million samples/sec)
Two two-channel, 12-bit, 1msps DACs
32 PWM outputs, 8 UART, 4 TWI (I2C) and 4 SPI channels, and a CRC generator module
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
- Resets the chip if it is not fed frequently enough (to reset if there is a hang)
Special microcontroller features
- Power-on reset and programmable brown-out detection
- Internal and external clock options with PLL and prescaler
- Programmable multilevel interrupt controller
- Five sleep modes
Programming and debug interfaces
- JTAG (IEEE 1149.1 compliant) interface, including boundary scan
- PDI (Program and Debug Interface)

Little endian
- When 32-bit values are saved the least significant 16 bits are saved first, in the lower address (and the most significant 16 bits are saved to the next higher address)
- Loading a single byte of the address register will always update the LSB byte while the MSB bytes are left unchanged
Program Memory
- All AVR CPU instructions are 16 bits wide, and each flash location is 16 bits wide

Data Memory
- Contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory, if available
- All 8 bits wide