Synchronization

• Two processors sharing an area of memory
  • P1 writes, then P2 reads
  • Data race if P1 and P2 don’t synchronize
    • Where results depend on order of access
• We can solve that using read write locks
  • Load exclusive register: LDXR
  • Store exclusive register: STXR
• To use
  • Execute LXDR then STXR with same address
  • If there is an intervening change to the address, store fails (communicated with an additional output register)
  • Only use register instruction in between
• Atomic operation: when you can read and write and be sure that nothing else is accessing the data at the same time

Implementations

Atomic swap (to test/set lock variable)

again: LDXR X10, [X20,#0]
	   STXR X23, X9, [X20] // X9 = status
       CBNZ X9, again 
	   ADD X23, XZR, X10   // X23 = loaded value

• Issue: unnecessary store instruction

Lock

	    ADDI X11, XZR, #1   // copy locked value
again:  LDXR X10 ,[X20,#0]  // read lock 
	    CBNZ X10, again     // check if is 0 yet
	    STXR X11, X9, [X20] // attemp to store
	    BNEZ X9,again       // branch if fails
Unlock: STUR XZR, [X20,#0]  // free lock