Multipliers

Array Multiplier

  • Shift and add principle
    • For
  • Overhead
    • Hardware: gates
      • 2-bit multiplications: 2-AND gates
      • n-bit additions: full adders
    • Delay:

Sequential Multiplier

  • Partial sums are accumulated stepwise
  • Notes
    • Y is stored in a partial sum register save 1 register
    • ‘logic shift’, i.e. fill right with 0s
  • Algorithm
    1. Load X,Y
    2. C←0, P←0
    3. Iterate n-times:
      1. if Y(0)=1
        1. then P←P+X
        2. else P←P+0
      2. shift (C,P,Y) 1 digit left
    4. Result is in (P,Y)

Signs

  • Sign Magnitude
    1. Compute magnitude and sign
    2. Multiply the magnitudes
    3. Compute the sign of the result
    4. Negate the result if negative
  • 2’s Complement
    • If
      • ‘Arithmetic shift’ (signed shift, sign extension) : shift left with sign instead of 0
      • Sign in position ; on overflow in → shift
    • If
      • Then is what was computed
      • We need to subtract through to get the correct result

Booth Multiplier

  • Optimization
    • No need to add when , only shift
    • It is not necessary to perform additions when there is a chain of 1‘s in y
      • We just need to subtract X at the begin of the chain and add X back at the end of the chain
        • Where is the first digit that is 1 and is the number of consecutive 1s (so is the last 1 in the chain)
  • Booth Recoding: is translated to
    1. is extended by
    2. is built as follows
  • Meaning of :
    • : shift right
    • (represented “S”): P –= x then right shift (begin of a chain of 1s)
    • (represented “A”) : P += X then right shift (end of a chain of 1s)
  • Requires an addition and subtraction for each chain
    • Weakness: when multiplier alternates between 0s and 1s
    • Can sometimes be avoided by switching the first and second operands